FIG. 1 is a cross-sectional view of a conventional MOS transistor. Referring to FIG. 1, the MOS transistor has a gate electrode 3 on a semiconductor substrate 1 with a gate oxide layer 2 interposed therebetween. Source/drain regions 4 and 5 are provided in the substrate 1 on opposite sides of the gate electrode 3. Carriers such electrons or holes are supplied to the source region 4 and removed from the drain region 5. The gate electrode 3 provides for forming a surface inversion layer, i.e., a channel, extending between the source region 4 and the drain region 5.
In scaling down MOS transistors to provide higher integration of semiconductor devices, the reduction in the length of the gate electrode may occur at a greater rate than reductions in the operating voltage of the device. With down scaling of the gate length, the influence of the source/drain upon the electric field or potential in the channel region of the MOS transistor may increase. This is, generally, called a “short channel effect” and may result in lowering of a threshold voltage of the transistor. This is because the channel region may be influenced by the depletion charge, the electric field and the potential distribution of the source/drain regions as well as the gate electrode.
In the MOS transistor of FIG. 1, the drain depletion layer 7 is widened in proportion to the increase in the drain voltage, so that the drain depletion layer 7 comes close to the source region 4. Thus, the drain depletion layer 7 and the source depletion layer 6 may connect to each other if the length of the gate electrode 7 is decreased. The electric field of the drain may eventually penetrate into the source region 4 and, thereby, reduce the potential energy barrier of the source junction. When this occurs, more majority carriers in the source region 4 have enough energy to overcome the barrier, and an increased current flows from the source region 4 to the drain region 5. This is often referred to as a “punchthrough” phenomenon. When punchthrough occurs, the drain current is not saturated but rapidly increased in the saturation region.
In conventional MOS transistor technology, a threshold voltage (Vt) adjusting implant is performed to provide a desired threshold voltage. For example, a p-type impurity such as boron (B) may be ion implanted in an NMOS transistor.
When the drain voltage is relatively low in a short-channel MOS transistor, the drain depletion layer does not extend to the source region, but the surface of the substrate is depleted to some degree by the gate electrode, thereby varying the height of the potential barrier near the source. This is commonly called “surface punchthrough.” The Vt-adjusting implant increases the doping concentration of the interface between the substrate and the gate oxide layer, thereby suppressing the surface punchthrough as well as adjusting the threshold voltage.
Methods of forming an anti-punchthrough region below the gate electrode are disclosed in Japanese Patent Laid Open Publication No. 11-214687 and U.S. Pat. Nos. 6,207,428, 5,926,712, 6,285,061.
In dynamic random access memory (DRAM) devices in which a unit memory cell has one transistor and one capacitor cell, a data restoring operation, i.e., a refresh for recharging the data charge is necessary because the data charge of the capacitor decreases due to the leakage current with the lapse of time. Typically, the cell transistor is an NMOS transistor. Therefore, when the ion implantation is performed at a high dose, the junction leakage current increases due to the high electric field at the pn junction where the n-type source/drain regions makes contact with the p+ region (i.e., anti-punchthrough region), resulting in the deterioration of the charge and may result in a need for more frequent refresh.
Methods of locally forming anti-punchthrough regions directly below the gate electrode are disclosed in U.S. Pat. Nos. 5,489,543 and 6,285,061.